1. Field of the Invention
The present invention relates to the field of electronic components, and more specifically to a method for manufacturing high-density electronic components on a substrate. The present invention also relates to structures obtained by this method.
2. Discussion of the Related Art
U.S. Pat. No. 6,399,502 describes a method for manufacturing the structure illustrated in FIG. 1.
In a semiconductor substrate 1, which corresponds to the upper portion of a bulk substrate or to a semiconductor layers resting on an insulating layer (SOI), a rectangular opening 3 is formed. Growths by successive alternated epitaxies of silicon-germanium (SiGe) layers 5, 9, 13 and silicon layers 7, 11, 15 which form on the main upper surface of substrate 1 and on the bottom and the lateral walls of opening 3 are then carried out. Last layer 15 may be made of a material other than silicon, for example, a dielectric, deposited in any appropriate fashion. Once these growths have been carried out, a chem-mech polishing (CMP) is performed to obtain the structure illustrated in FIG. 1 having a planar main upper surface, at the level of which are exposed vertical portions of layers 5, 9, and 13 and of layers 7, 11, and 15 of the stack formed in opening 3.
This method enables obtaining, at the surface of substrate 1, a horizontal succession of patterns formed of different materials, such patterns having small widths and being well controllable. Indeed, silicon-germanium layers 5, 9, and 13 and silicon layers 7, 11, and 15 being formed by epitaxial growths in the bottom and on the lateral walls of opening 3, the vertical portions of these layers are exposed, once the polishing has been carried out, at the surface level of the structure of FIG. 1. The thicknesses of the successive layers become the widths of the patterns formed on the top of the device shown in FIG. 1.
In the art, the widths of patterns buried at the surface of a substrate are generally obtained by photolithographic etch operations. Now, the maskings needed in such methods do not enable obtaining areas of dimensions smaller than a given threshold. The above-described method, which uses well-controlled epitaxial growths, enables obtaining, on the surface of a structure, patterns having dimensions which may be extremely small, for example, on the order of one nanometer.
In U.S. Pat. No. 6,399,502, the portions of the successively-formed layers are directly used to obtain quantum wires, detectors based on silicon-germanium and on silicon, or silicon-based laser structures.